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[IEEE] Design and Implementation of Low Power Posit Arithmetic Unit for Efficient Hardware Accelerators

GANESH6993 Post time 2024-6-7 11:24:59 | Show all posts |Read mode
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journal：2022 10th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC)

Authors：Mohammed Essam; Ahmed Shalaby; Mohamed Taher

Published date：2022-12-19

DOI：10.1109/jac-ecc56395.2022.10043893

PDF link：https://ieeexplore.ieee.org/stampPDF/getPDF.jsp?arnumber=10043893

Article link：http://dx.doi.org/10.1109/jac-ecc56395.2022.10043893

Article Source：IEEE。


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